1. Field of the Invention
The present invention relates to semiconductor memory devices, and in particular to semiconductor memory devices such as DRAMs (dynamic random access memories) provided with a bit line precharge voltage generating device that is capable of quickly performing a precharge operation if the precharge potential of the bit lines differs from a middle potential of the bit line pair.
2. Description of the Related Art
The circuit configuration and the operation of a semiconductor memory device in which a conventional bit line precharge voltage generating device is mounted are described below with reference to the drawings.
FIG. 19 shows a function block diagram of an ordinary DRAM 5000. Numeral 4000 denotes a memory array, 4001 denotes memory array blocks, 4002 denotes a power source block, 4003 denotes a row controller, 4004 denotes a column controller, 4005 denotes a control circuit, and 4006 denotes an I/O buffer.
The memory array 4000 includes a plurality of memory array blocks 4001. The power source block 4002 supplies the voltage necessary for the memory array 4000, such as the bit line precharge voltage VBP and the memory cell plate voltage VCP, to each memory array block 4001. Each memory array block 4001 is controlled by a bit line precharge signal NEQ, sense amplifier activation signals SAN and SAP, and a word line drive signal WL [63:0 ], which are input from the row controller 4003. Further, the memory array blocks 4001 are each connected to the column controller 4004.
The row controller 4003 receives the access control signal SE and the row address signal RAD from the control circuit 4005. The column controller 4004 receives the write enable signal WEN and the column address signal CAD from the control circuit 4005.
The control circuit 4005 receives an outside clock signal CLK, a row address strobe signal NRAS, a column address strobe signal NCAS, a write control signal NWE, an address ADDR, and a refresh control signal REF.
The column controller 4004 is connected to the I/O buffer 4006. The I/O buffer 4006 receives data input signals DI and outputs data output signals DO.
FIG. 20 is a circuit diagram of the memory array blocks 4001. Numeral 4100 is a memory cell, 4101 is a sense amplifier, 4102 is a precharge circuit, BL[n](n=0,1, . . . ) are bit lines, and /BL[n](n=0,1, . . . ) are bit lines paired with the bit lines BL[n]. The memory cell 4100 is made of a capacitor 4104 and an access transistor 4103, which is a p-channel transistor. The source of the access transistor 4103 is connected to the bit line BL[n] or /BL[n], the drain of the access transistor 4103 is connected to one node of the capacitor 4104, and the gate of the access transistor 4103 is connected to a word line drive signal WL[n] line. The other node of the capacitor 4104 is connected to the memory cell plate voltage VCP.
The sense amplifier 4101 is an ordinary cross-coupled sense amplifier, and is connected to the pair of bit lines BL[n] and /BL[n]. The sense amplifier 4101 is controlled by the sense amplifier activation signals SAN and SAP. The precharge circuit 4102 is made of three p-channel transistors. These are a transistor whose source is connected to the bit line BL[n], whose drain is connected to the bit line /BL[n], and whose gate is connected to the bit line precharge signal NEQ line, a transistor whose source is connected to the bit line BL[n], whose drain is connected to the bit line precharge voltage VBP, and whose gate is connected to the bit line precharge signal NEQ line, and a transistor whose source is connected to the bit line precharge voltage VBP, whose drain is connected to the bit line /BL[n], and whose gate is connected to the bit line precharge signal NEQ line.
FIG. 21 shows the power source wiring network of the bit line precharge voltage VBP. Bit line precharge power lines VBP[n] are arranged on the memory cell array 4000 so as to supply the bit line precharge voltage VBP from the precharge voltage generating circuit 4200 to the precharge circuits 4102 that are arranged in each memory array block 4001 (see FIG. 20). The bit line precharge power lines VBP[n] are expressed as VBP[0], VBP[1], . . . VBP[n] in order from the side near the precharge voltage generating circuit 4200. The bit line precharge power lines VBP[n] are disposed in the column direction as the wiring layer of the upper layer of each memory array block 4001 (in FIG. 21, shown by the solid lines). The bit line precharge power lines VBP[n] are connected to one another in the row direction by metal wiring (in FIG. 21, shown by the dashed lines) so as to lower the impedance. In this manner, the bit line precharge power lines VBP[n] are arranged in a matrix, and the thickest possible wiring is used. The bit line precharge power line VBP[0] is connected to the precharge voltage generating circuit 4200.
FIG. 22 shows a conventional precharge voltage generating circuit 4200. Numeral 4300 denotes a reference voltage generating circuit, 4301 denotes an operational amplifier, and 4302 denotes a p-channel transistor. VBPREF is the bit line precharge reference voltage, VOUT is the bit line precharge hold voltage, and PEN is the driver enable signal. The reference voltage generating circuit 4300 generates the bit line precharge reference voltage VBPREF and the bit line precharge hold voltage VOUT. The bit line precharge reference voltage VBPREF is connected to the −input of the operational amplifier 4301 and the bit line precharge hold voltage VOUT is connected to the bit line precharge power line VBP[0]. The +input of the operational amplifier 4301 is connected to the bit line precharge power line VBP[0]. The output of the operational amplifier 4301 is the driver enable signal PEN, and is input to the gate of the p-channel transistor 4302. The source of the p-channel transistor 4302 is connected to the VDD, and the drain of the p-channel transistor 4302 is connected to the bit line precharge power line VBP[0]. Thus the operational amplifier 4301 and the p-channel transistor 4302 compose a comparing and driving circuit.
FIG. 23 shows a circuit diagram of the reference voltage generating circuit 4300. Numeral 4400 denotes a resistor (resistor R1) and 4401 denotes a resistor (resistor R2). The circuit configuration is that of an ordinary ½ VDD generating circuit, which is described in detail in “Super LSI Memories” (authored by Kiyoo Itoh, Baifukan), and thus a detailed description thereof is omitted. The output stages are for generating the bit line precharge reference voltage VBPEREF and the bit line precharge hold voltage VOUT. The voltage that is output is VOUT=VBPREF=R2/(R1+R2)×VDD. Resistance values that are sufficiently larger than the on resistance of the transistors making up this circuit can be used as the values for R1 and R2.
The operational amplifier 4301 is an ordinary, current mirror load-type differential operational circuit such as that shown in FIG. 24. AMPEN is a differential amplifier control signal. As the differential input, the bit line precharge reference voltage VBPREF is connected to the −input and the bit line precharge power line VBP[0] is connected to the +input. The output is the driver enable signal PEN. When the differential amplifier control signal AMPEN is the VDD level, then the operational amplifier 4301 is in an operational state, and when it is the VSS level, the operational amplifier 4301 is in a stopped state, and current consumption can be reduced. As this circuit is well known, a more detailed explanation of its operation will be omitted.
FIG. 25 shows the operation timing and the internal voltage timing of a DRAM having the above configuration. Here, only the read operation is shown. In a non-operational state (stand-by), all word lines WL[n] are at a high level, all access transistors 4103 are off, and an arbitrary voltage is held in the capacitor 4104. Also, the bit line precharge signal NEQ is at a low level, all precharge circuits 4102 are in an operating state, and all bit lines BL[n] and /BL[n] are charged to the bit line precharge voltage VBP.
At the rising edge of the outside clock signal, the word line selection operation is started by setting the row address strobe signal NRAS to a low level and receiving a row address as the address ADDR. When the word line selection operation is started, the bit line precharge signal NEQ that is input to the arbitrary memory array block 4001 determined by the row address that is input is set to a high level. When the bit line precharge signal NEQ is set to a high level, the corresponding precharge circuit 4102 is stopped. Also, the differential amplifier control signal AMPEN is set to a high level and the operational amplifier is activated in order to prepare for the precharge operation.
Then, the word line WL[n] that is determined by the input row address is set to a low level (VSS), the plurality of memory cells 4100 that are connected thereto are turned on, and the voltage that is held in the capacitor 4104 is read to the connected bit line BL[n] or /BL[n]. Next, the sense amplifier activation signal SAN is set to a low level (VSS) and the sense amplifier activation signal SAP is set to a high level (VDD) so that the sense amplifier 4101 is activated. When the sense amplifier 4101 is activated, the bit line BL[n] or /BL[n] is charged to a low level (VSS) or a high level (VSS) based on the potential that is read to the bit line BL[n] or /BL[n].
Here, the word line WL[n] to which the memory cell 4100 that is read out is connected is set to a low level (VSS), so that the potential of the connected bit lines BL[n], /BL[n] is once again written into the capacitor 4104. The access transistor 4103 is a p-channel transistor, and therefore a potential of Vtp (the threshold voltage of a p-channel transistor) is written as the low level and VDD is written as the high level. That is, the voltage that is written to the capacitor 4104 is VDD if high level and Vtp if low level. In order to read out both the high level read potential and the low level read potential with an optimal margin, the bit line precharge voltage VBP is ideally ½(VDD+Vtp), which is the mean value between them.
Then, by setting the column address strobe signal NCAS to a low level and inputting a column address as the address ADDR in synchronization with the rising edge of the outside clock signal CLK, the column controller 4004 is activated and data are output as data output signals DO.
Next, by setting the row address strobe signal NRAS and the column address strobe signal NCAS to a high level in synchronization with the rising edge of the outside clock signal CLK, the precharge operation is started. When the precharge operation is started, the word line WL[n] is set from a low level to a high level, the access transistor 4103 is turned off, and a charge is held in the capacitor 4104. To prepare for the next read operation, the bit line precharge signal NEQ is set to a low level and the precharge circuit 4102 is activated.
When the precharge circuit 4102 is activated, the potentials of the bit lines BL[n], /BL[n], which are set to the potentials VDD and VSS, are equalized by the sense amplifier 4101 and charged to a potential of ½ VDD. The precharge circuit 4102 simultaneously is connected to the bit line precharge power line VBP[n] corresponding to the bit lines BL[n], /BL[n] so as to charge to it the bit line precharge voltage VBP.
FIG. 26 shows the operation of the bit line precharge power line VBP[n] according to this conventional configuration during activation of the precharge circuit 4102. As mentioned previously, when the bit line precharge signal NEQ is set to a low level and the precharge circuit 4102 is activated, the activated bit lines BL[n], /BL[n], which are connected to the bit line precharge power line VBP[n], current is consumed and a drop in voltage occurs. The bit line precharge power line VBP[n] and the bit line precharge power line VBP[0] are connected in a lattice so as to lower the impedance, and transmission of the voltage is delayed by about several ns.
The bit line precharge power line VBP[0] is connected to the precharge voltage generating circuit 4200. At the point that the bit line precharge power line VBP[0] becomes a lower voltage than the bit line precharge reference voltage VBPREF, the driver enable signal PEN, which is output by the operational amplifier 4301, becomes lower toward the low level and the p-channel transistor 4302 is turned on, so that a high level voltage is supplied to the bit line precharge power line VBP[0]. At the point that the high level voltage supplied to the bit line precharge power line VBP[0] has increased the voltage to a higher voltage than the bit line precharge reference voltage VBPREF, the driver enable signal PEN, which is output by the operational amplifier 4301, rises toward the high level and the p-channel transistor 4302 is turned off.
Because the p-channel transistor 4302 requires current capabilities and is relatively large in size (W=50 μm or more), the drive enabler signal PEN is delayed with respect to the relationship between the bit line precharge power line VBP[0] and the bit line precharge reference voltage VBPREF, and as shown in FIG. 26, the current ia that flows through the p-channel transistor 4302 is delayed.
To achieve a stable read during the next read operation, the voltage of the bit lines BL[n], /BL[n] must be kept within a predetermined range. However, with the conventional bit line precharge voltage generating device 4200, the operation of the operational amplifier 4301 is slow and it is difficult to increase the speed of the precharge operation, and this was a problem. Although the speed of the precharge operation can be raised by increasing the current consumption of the operational amplifier 4301, the increase in power consumption becomes a problem.